Exemplary embodiments relate generally to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having an air gap, and a method of manufacturing the same.
Recently, as the degree of integration of semiconductor devices has been enhanced, a defective rate of semiconductor devices has been increased. Problems of the related art will be described in detail with reference to FIGS. 1A to 1D.
FIGS. 1A to 1D are cross-sectional views illustrating a method of manufacturing a memory cell of a NAND flash memory device according to the related art. FIGS. 1A to 1D are cross-sectional views of memory cells of a NAND flash memory device taken along gate lines.
Referring to FIG. 1A, a semiconductor layer 101 includes isolation regions where trenches 109 are formed, and active regions A are divided by the trenches 109. A tunnel insulating layer 103 and a first conductive film 105a for a floating gate are stacked on each of the active regions A. The tunnel insulating layer 103 and the first conductive film 105a may remain only under isolation masks 107 that open the regions in which the trenches 109 are to be formed.
Widths of the active regions A and widths of the trenches 109 are reduced as the degree of integration is increased. Thus, the active regions A and the trenches 109 of a semiconductor device having a high degree of integration may be formed to have a very narrow width.
Referring to FIG. 1B, a sufficient amount of an isolation layer 111a is formed on the entire structure so that the trenches 109 are filled. Here, if the interior of the trenches 109 formed to have narrow widths is not fully filled with the isolation layer 111a, air gaps 113 may be generated in the isolation layer 111a within the trenches 109. Here, when the air gaps 113 are formed, the air gaps 113 may be formed to be irregular in position and size in each trench 109, rather than being uniform.
Referring to FIG. 1C, the isolation layer 111a is planarized until the isolation masks 107 are exposed, and the isolation masks 107 are subsequently removed. Subsequently, the height of the isolation layer 111a is lowered through an etching process so that upper sidewalls of the first conductive film 105a are exposed. Accordingly, the isolation layer 111b having a target height is formed. During the etching process performed to adjust the height of the isolation layer 111b as a target height, the air gap 113 may be exposed.
Referring to FIG. 1D, a dielectric film 121 is formed on a surface of the entire structure that includes the isolation layer 111b, and a second conductive film 123 for a control gate is formed on the dielectric film 121. The second conductive film 123 is formed to cover spaces between the first conductive films 105a (shown in FIG. 1C). Thereafter, the second conductive film 123, the dielectric film 121, and the first conductive film 105a are etched through an etching process that uses the gate masks 125 as an etch barrier. Accordingly, the second conductive film 123 is patterned as a gate lines in a direction crossing the active regions A or the isolation layers 111b. The first conductive film 105b remains as a floating gate in the crossing of the gate lines and the active regions A.
In the above, when the dielectric film 121 and the second conductive film 123 are formed, and if the air gap 113 is exposed, the interior of the air gap 113 may be filled with the dielectric film 121 and the second conductive film 123. As a result, during an etching process to form the gate lines, the second conductive film 123 within the air gap 113 may not be removed and the gate lines may be connected, rather than, being separated to cause a defect.
Meanwhile, without the air gap 113, the space between the active region A and the floating gate 105b and the space between the active region A and the second conductive film 123 as a gate line would be filled with the isolation layer 111b. In this case, first capacitance between the active region A and the floating gate 105b and second capacitance between the active region A and the gate line in an adjacent memory cell are determined by permittivity of the isolation layer 111b. The first and second capacitances depending on the permittivity of the isolation layer 111b are increased as the degree of integration is enhanced. Thus, a malfunction rate may be increased due to interference between the active region A and the floating gate 105b and interference between the active region A and the gate line.